1. There are _________ types of reset operations in SRC

2. _____________ controller controls the sequence of the flow of microinstructions

3. Prefetching can be considered a primitive form of-------------

4. An “assembler” that runs on one processor and translates an assembly language program written for another processor into the machine language of the other processor is called a ----------------

5. What is the working of Processor Status Word (PSW)?

6. The processor must have a way of saving information about its state or context so that it can be restored upon return from the -------------

7. _____________all memory systems are dumb, in that they respond to only two commands: read or write

8. The instruction ___________ will load the register R3 with the contenets of the m\emory location M [PC+56]

9. The instruction ---------------will load the register R3 with the contents of the memory location M [PC+56]

10. _________control signals enable the input to the PC for receiving a value that is currently on the internal processor bus

11. _______ operation is required to change the processor‟s state to a known, defined value

12. The external interface of FALCON-A consists of a ______address bus and ______a data bus.

13. What functionality is performed by the instruction “lar R3, 36” of SRC?

14. Flip-flop is a ____________device, capable of storing one bit of Information

15. Execution time of a program with respect to the processor is calculated as:

16. For any of the instructions that are a part of the instruction set of the SRC, there are cerain_________required; which may be used to select the appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location

17. The data movement instructions ___________ data within the machine and to or from input/output devices

18. Register-register instructions use ____________ memory operands out of a total of 3 operands

19. FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC _____wide.

20. Which one of the following is the memory organization of EAGLE processor?

21. ___________ or Branch instructions affect the order in which instructions are performed, or control the flow of the program

22. “If P = 1, then load the contents of register R1 into register R2”. This statement can be written in RTL as:

23. Which operator is used to „name‟ registers, or part of registers, in the Register Transfer Language? Select correct option

24. __________ enable the input to the PC for receiving a value that is currently on the internal processor bus.

25. Which one of the following registers holds the address of the next instruction to be executed?

26. P: R3 ¬ R5 MAR ¬ IR These two are instructions written using RTL .If these two operations is to occur simultaneously then which symbol will we use to separate them so that it becomes a correct statement with the condition that two operations occur simultaneously?

27. The code size of 2-address instruction is ________________.

28. To access an operand in memory, the CPU must first generate an address, which it then issues to the

29. Type A of SRC has which of the following instructions? A) andi, instruction b) No operation or nop instruction c) lar instruction d) ldr instruction e) Stop operation or stop instruction

30. FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC is __________ wide.